The Price of Performance

In the late 1990s, our research group at DEC was one of a growing number of
teams advocating the CMP (chip multiprocessor) as an alternative to highly
complex single-threaded CPUs. We were designing the Piranha system,1 which
was a radical point in the CMP design space in that we used very simple cores
(similar to the early RISC designs of the late ’80s) to provide a higher
level of thread-level parallelism. Our main goal was to achieve the best commercial
workload performance for a given silicon budget.